
// Library name: VLSI_PROJECT
// Cell name: amk_inverter
// View name: schematic
subckt amk_inverter VDD VSS in out
    T1 (out in VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (out in VSS VSS) lpnfet l=120.0n w=160.0n nf=1 m=1 par=1 ngcon=1 \
        ad=8.8e-14 as=8.8e-14 pd=1.42u ps=1.42u nrd=1.5652 nrs=1.5652 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_inverter
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_nand
// View name: schematic
subckt amk_nand VDD VSS a b z
    T1 (z b VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T3 (z a VDD VDD) lppfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T2 (net17 b VSS VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    T0 (z a net17 VSS) lpnfet l=120.0n w=320.0n nf=1 m=1 par=1 ngcon=1 \
        ad=1.76e-13 as=1.76e-13 pd=1.74u ps=1.74u nrd=0.5625 nrs=0.5625 \
        rf_rsub=1 plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_nand
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: dac_latch
// View name: schematic
subckt dac_latch D Q VDD VSS clk
    I4 (VDD VSS D net7) amk_inverter
    I3 (VDD VSS Q net22 net15) amk_nand
    I2 (VDD VSS net27 net15 Q) amk_nand
    I1 (VDD VSS clk net7 net22) amk_nand
    I0 (VDD VSS D clk net27) amk_nand
ends dac_latch
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: simple_switch
// View name: schematic
subckt simple_switch VDD VSS cntrl in out
    T0 (out cntrl in VSS) lpnfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
    I0 (VDD VSS cntrl net8) amk_inverter
    T1 (out net8 in VDD) lppfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends simple_switch
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: amk_mux
// View name: schematic
subckt amk_mux VDD VSS in out sel
    I3 (VDD VSS sel net021) amk_inverter
    I2 (VDD VSS sel in out) simple_switch
    T0 (in net021 VSS VSS) lpnfet l=120.0n w=1u nf=1 m=1 par=1 ngcon=1 \
        ad=5.5e-13 as=5.5e-13 pd=3.1u ps=3.1u nrd=0.18 nrs=0.18 rf_rsub=1 \
        plnest=-1 plorient=-1 pld200=-1 pwd100=-1 lstis=1 lnws=0 \
        rgatemod=0 rbodymod=0 panw1=0p panw2=0p panw3=0p panw4=0p panw5=0p \
        panw6=0p panw7=0p panw8=0p panw9=0p panw10=0p sa=5.5e-07 \
        sb=5.5e-07 sd=0u dtemp=0
ends amk_mux
// End of subcircuit definition.

// Library name: VLSI_PROJECT
// Cell name: current_scaler_res
// View name: schematic
R9 (net150 net0202) resistor r=0
R15 (out net068) resistor r=0
R11 (net138 net0192) resistor r=0
R7 (net180 net0227) resistor r=0
R8 (net0162 net0182) resistor r=0
R10 (net144 net0197) resistor r=0
R12 (net132 net0187) resistor r=0
R6 (net174 net0222) resistor r=0
R5 (net168 net0217) resistor r=0
R4 (net162 net0212) resistor r=0
R3 (net156 net0207) resistor r=0
I55 (in7 in7_out VDD VSS clock) dac_latch
I56 (in8 in8_out VDD VSS clock) dac_latch
I49 (in5 in5_out VDD VSS clock) dac_latch
I57 (in9 in9_out VDD VSS clock) dac_latch
I54 (in0 in0_out VDD VSS clock) dac_latch
I53 (in1 in1_out VDD VSS clock) dac_latch
I52 (in2 in2_out VDD VSS clock) dac_latch
I63 (in3 in3_out VDD VSS clock) dac_latch
I50 (in4 in4_out VDD VSS clock) dac_latch
I47 (in6 in6_out VDD VSS clock) dac_latch
nwres20 (net71 VSS VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres19 (net74 net71 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres18 (net77 net74 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres17 (net80 net77 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres16 (net83 net80 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres15 (net86 net83 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres14 (net89 net86 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres13 (net92 net89 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres12 (net122 net92 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres11 (net71 net132 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres10 (net74 net138 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres9 (net77 net144 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres8 (net80 net150 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres7 (net83 net156 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres6 (net86 net162 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres5 (net89 net168 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres4 (net92 net174 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres2 (net068 net122 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=150 \
        dtemp=0 rsx=50 sh=1
nwres3 (net122 net180 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
nwres0 (net068 net0162 VSS) nwres r=2.01819K w=3u l=10u m=1 par=1 sbar=300 \
        dtemp=0 rsx=50 sh=1
I9 (VDD VSS net0187 Vref in0_out) amk_mux
I8 (VDD VSS net0192 Vref in1_out) amk_mux
I7 (VDD VSS net0197 Vref in2_out) amk_mux
I6 (VDD VSS net0202 Vref in3_out) amk_mux
I5 (VDD VSS net0207 Vref in4_out) amk_mux
I4 (VDD VSS net0212 Vref in5_out) amk_mux
I3 (VDD VSS net0217 Vref in6_out) amk_mux
I2 (VDD VSS net0222 Vref in7_out) amk_mux
I1 (VDD VSS net0227 Vref in8_out) amk_mux
I10 (VDD VSS net0182 Vref in9_out) amk_mux
